ECL level/CMOS level logic signal interfacing device

ABSTRACT

An ECL level/CMOS level logic signal interfacing device includes, connected in cascade, a circuit for generating an in-phase relationship with an ECL level input signal, a threshold inverter circuit receiving the in-phase signal at an inverter input and delivering an inverted in-phase signal, a shaping inverter circuit receiving the inverted in-phase signal and outputting a calibrated in-phase signal, and an output amplifier circuit receiving the calibrated in-phase signal and outputting an output signal to the CMOS level in phase relationship with the ECL level input signal. The circuits are supplied with a CMOS level supply voltage relative to a reference voltage.

The invention relates to an ECL level/CMOS level logic-signalinterfacing device.

In current integrated circuits, especially logic circuits, it isessential to allow switching from a low logic level to a high logiclevel, or vice versa, within a small switching amplitude range.

In particular in so-called ECL (Emitter Coupled Logic) structures, theswitching between low and high logic levels is defined between 3.2 V(low level) and 4.1 V (high level).

However, this type of circuit, which is being used more and more, posesthe problem of the compatibility of these logic levels with the logiclevels of the CMOS integrated circuits for which the low logic level isless than 1 V and the high logic level substantially equal to 5 V. Thecompatibility problem posed relates not only to the values of the supplyvoltages for these circuits but also to the continuity of transmissionof the logic information because, especially, of the risk of ambiguitycaused by the lack of discrimination between the ECL logic levels andthe CMOS logic levels.

Various solutions have been proposed in a similar context relating tothe lack of compatibility between BTL logic levels, low-voltage logiccircuits, 1.1 V low logic level, 1.9 V high logic level and TTL(Transistor Transistor Logic) or CMOS. One envisaged solution within theaforementioned context may consist in generating a common thresholdvoltage, intermediate between the TTL and CMOS high logic level and lowlogic level, and in discriminating these logic levels from thisthreshold value.

This solution is satisfactory, but it has, however, the followingdrawbacks:

presence of an added structure which can be used to generate the commonthreshold voltage and to discriminate between the aforementioned logiclevels;

occupation of a large area in the case of integrating this addedstructure in the form of an integrated circuit and correspondingoccupation of silicon. Transposing such a solution to ECL logic circuitsis therefore not to be desired because of the persistence of theaforementioned drawbacks.

The object of the present invention is to remedy these drawbacks byvirtue of the use of an ECL/CMOS level logic-signal interfacing devicein which the use of any common threshold voltage and of discriminationfrom this threshold voltage is dispensed with.

Another object of the present invention is also the use of an ECL/CMOSlevel logic-signal interfacing device in which the continuity oftransmission of the logic information is provided by the use oftransitions between voltage values of the low and high logic levelshaving compatible and gradually changing amplitudes.

The ECL level/CMOS level logic-signal interfacing device, the subject ofthe present invention, is noteworthy in that it comprises, connected incascade and supplied with a CMOS level supply voltage relative to areference voltage, a circuit for generating a signal in phase with theECL level input signal, this in-phase signal having an amplitude greaterthan that of the input signal and a mean amplitude value greater thanthat of the ECL level input signal, a threshold inverter circuit, thethreshold value of which is substantially equal to the mean amplitudevalue of the in-phase signal, this inverter circuit receiving on aninverting input the in-phase signal and delivering an inverted signal, ashaping inverter circuit receiving the inverted in-phase signal anddelivering a calibrated in-phase signal and an output amplifier circuitreceiving the calibrated in-phase signal and delivering an outputsignal, at the CMOS level, in phase with the input signal.

Such a device finds application in the manufacture of integratedcircuits or of components for integrated circuits.

It will be more clearly understood on reading the description and onexamining the drawings appended hereto, in which:

FIG. 1 represents a functional schematic diagram of the device which isthe subject of the present invention;

FIG. 2a represents, by way of nonlimiting example, a diagram of oneembodiment of the device which is the subject of the invention,according to FIG. 1, in CMOS technology.

FIGS. 2b1 to 2b4 represent signal timing diagrams obtained at the testpoints in FIG. 2a;

FIG. 3 represents a diagram of a particular embodiment of the devicewhich is the subject of the invention, in which a differential mode ofinputing two ECL signals is used.

A more detailed description of the ECL level/CMOS level logic-signalinterfacing device, which is the subject of the present invention, willnow be given in conjunction with FIG. 1.

The device, which is the subject of the invention, shown in FIG. 1 isnormally supplied with a CMOS level supply voltage, denoted by VCC,relative to a reference voltage VSS.

It is composed of a series of modules connected in cascade, thesemodules consisting, in succession, of a circuit 1 for generating asignal in phase with the ECL level input signal, this input signal beingdenoted I. In accordance with one particularly advantageouscharacteristic of the device which is the subject of the presentinvention, the in-phase signal has an amplitude greater than that of theinput signal I and a mean amplitude value greater than that of this sameECL level input signal.

A threshold inverter circuit 2 is provided in which the in-phase signaldelivered by the circuit 1 is received on an inverting input, thisthreshold inverter circuit 2 having a switching threshold, the thresholdvalue of which is substantially equal to the aforementioned meanamplitude value of the in-phase signal. The threshold inverter circuit 2delivers an inverted in-phase signal.

A shaping inverter circuit 3 is provided, this shaping inverter circuit3 being connected to the threshold inverter circuit 2 so as to receivethe inverted in-phase signal delivered by the latter. It delivers acalibrated in-phase signal.

Finally, an output amplifier circuit 4 is provided, this circuit beingconnected to the shaping inverter circuit 3, this output amplifiercircuit receiving the calibrated in-phase signal delivered by the latterand delivering an output signal, denoted by O, to the CMOS level, thissignal being substantially in phase with the input signal I.

Thus, as furthermore shown in FIG. 1 and particularly advantageously,the circuit 1 for generating an in-phase signal, the threshold invertercircuit 2 and the shaping circuit 3 may include a control circuitreceiving a control signal E making it possible to reduce thesteady-state electric-power consumption, in standby mode, of theinterfacing device which is the subject of the present invention.According to an advantageous additional characteristic, it may bepointed out that the aforementioned control circuit which can be used toapply, onto the output of the amplifier circuit 4, a CMOS level outputsignal making it possible to inhibit the steady-state consumption of anydownstream circuit connected to this output and in particular of CMOSmemory matrices connected to the device according to the invention asshown in FIG. 1, in order to provide the interfacing between ECL inputsignals and CMOS-type memory units, for example.

The operating mode of the control circuits used to carry out theaforementioned functions of reducing the steady-state electric-powerconsumption will be described later in the description.

Thus, as furthermore shown in FIG. 1, it may be pointed out that thecircuit 1 for generating a signal in phase with the input signal Icomprises a current comparator circuit formed by an input branch,denoted by 11, and an amplification branch, denoted by 12, the twobranches being connected in parallel between the CMOS level supplyvoltage VCC and a common point, denoted by 13. The input branch and theamplification branch are each formed by a current generator, denotedrespectively by 110 and 120, and a voltage-adjustable resistance,respectively 111 and 121. The output of the current generator 110 of theinput branch 11 is coupled to an input for controlling the currentgenerator 120 of the amplification branch 12. Furthermore, the controlinput of the voltage-adjustable resistance 111 of the input branch 11 isconnected to an input terminal which receives the input signal I, whilethe input for controlling the adjustable resistance 121 of theamplification branch 12 is connected to the CMOS level supply voltageVCC.

Finally, as shown in FIG. 1, the circuit 1 for generating the signal inphase with the input signal comprises an attenuated current source,denoted by 14, which is connected in cascade with the input branch andthe amplification branch in parallel, that is to say between the commonpoint 13 and the reference voltage VSS.

The circuit 1 for generating the signal in phase with the input signalmakes it possible to deliver the in-phase voltage at the point ofconnection between the current generator 120 and the voltage-adjustableresistance 121 of the amplification branch 12, as will be describedlater in the description.

As furthermore shown in FIG. 1, the shaping inverter circuit 3advantageously comprises a single-output voltage comparator, denoted by30, receiving on its negative and positive comparison inputsrespectively the inverted in-phase signal delivered by the invertercircuit 2 and the in-phase signal delivered by the circuit 1 forgenerating a signal in phase with the ECL level input signal. Thesingle-output voltage comparator circuit 30 delivers a comparison signalwith respect to the aforementioned in-phase signal and theaforementioned inverted in-phase signal.

The shaping inverter circuit 1 also comprises a shaping inverter module31 proper receiving the comparison signal delivered by the single-outputvoltage comparator 30, the comparison signal being with respect to thein-phase signal and with respect to the inverted in-phase signal, anddelivering the calibrated in-phase signal.

A more detailed description of the constituent elements of the devicewhich is the subject of the present invention, in an embodiment in CMOStechnology, will now be given in conjunction with FIG. 2a.

In the embodiment in question, it should be pointed out that, as per theconventional representation, the electrode of the MOS transistors whichis assigned a dot represents the drain electrode of this MOS transistor.

As shown in the aforementioned FIG. 2a, it should be pointed out thatthe current generator 110 of the input branch 11 of the constituentcurrent comparator circuit of the circuit 1 for generating a signal inphase with the input signal is formed by two PMOS transistors connectedin parallel, bearing the reference TP18i and TP40, is connected betweenthe supply voltage VCC and the common point 11 which in fact constitutesa first test point a.

Likewise, it should be pointed out that the current generator circuit120 of the amplification branch 12 consists of a PMOS transistor bearingthe reference TP4ecl. The gate electrodes of the aforementioned PMOStransistors 120 are interconnected and linked to the point 11constituting the test point a.

Furthermore, the voltage-adjustable resistance 111 of the input branch11 consists of two NMOS transistors in parallel, bearing the referenceTN8ecl, TN1ecl, these transistors thus being interconnected between thepoint constituting the test point a and the common point 13,constituting a second test point b. The gate electrodes of the NMOStransistors, TN8ecl and TN1ecl, are connected to an input terminal whichreceives the ECL input signal referenced I.

Likewise, it should be pointed out that the voltage-adjustableresistance 121 is formed by two NMOS transistors connected in parallelbetween the source electrode of the constituent PMOS transistor 120 ofthe current generator 120 and the aforementioned common point 13constituting the second test point b. It should be pointed out that thecommon point formed by the drain electrodes of the two NMOS transistorsbearing the reference TN17i and TN16i forming the voltage-adjustableresistance 121 constitutes a third test point c.

Furthermore, the attenuated current source 14 is formed by a first and asecond NMOS transistor, referenced TN15i and TN12i, these beingconnected in parallel between the common point 13 constituting the testpoint b and the reference voltage VSS. The base electrodes of the twoaforementioned NMOS transistors forming a current source are connectedby their gate electrode to an attenuation control module delivering anattenuation control voltage to the gate electrode of the NMOStransistors TN15i and TN12i.

As shown in the same FIG. 2a, it should be pointed out that theattenuation control module comprises a current source formed by a firstand a second PMOS transistor which are connected in parallel between theCMOS level supply voltage VCC and a first common point 141. The PMOStransistors are referenced TP8o, TP12o. The base electrode of theaforementioned first and second PMOS transistors is connected to thefirst common point 141, which delivers a substantially constant current.

The attenuation control module also comprises a resistance formed by aPMOS transistor and an NMOS transistor which are connected in parallelbetween a second common point 142 and the reference voltage VSS, thetransistors bearing the reference TP3ecl, TN7ecl. The gate electrode ofthe transistor TN7ecl is connected to the supply voltage VCC and that ofthe transistor TP3ecl is connected to the reference voltage VSS.

Furthermore, a voltage generator circuit is formed by a first and asecond NMOS transistor, these being referenced TN6i, TN9i and connectedin parallel between the first common point 141 and the second commonpoint 142. The gate electrode of the aforementioned first and secondNMOS transistors is connected to a third common point, 143, whichconstitutes the test point i and to which is interconnected the gateelectrode of the first and second NMOS transistors bearing thereferences TN15i and TN12i forming the current generator constitutingthe attenuated current source 14.

Furthermore, the voltage generator circuit comprises, on the one hand, afirst and second PMOS transistor which are connected in parallel,bearing the reference TP1o, TP0o, between the CMOS level supply voltageVCC and the fourth common point 143. The gate electrode of theaforementioned PMOS transistors is connected to the gate electrode ofthe first and second PMOS transistors TP8o, TP12o, constituting thecurrent source, and, on the other hand, an NMOS transistor, denoted byTN25i, connected between the fourth common point 143 constituting thetest point i and the reference voltage VSS, the gate electrode of theNMOS transistor, TN25i, being connected to the third common point 143and delivering the attenuation control voltage to the gate electrode ofthe transistors TN15i, TN12i.

With regard to the threshold inverter circuit 2, it should be pointedout that this may comprise, as shown in FIG. 2a, a first and a secondPMOS transistor, referenced TP7i, TP1ecl, which are connected inparallel between the CMOS supply voltage VCC and a common pointconstituting a test point e. The gate electrodes of the aforementionedfirst and second PMOS transistors are connected onto the output of thecircuit 1 for generating an in-phase signal and receive the lattersignal.

An NMOS transistor, bearing the reference TN3ecl, is connected incascade between the common point forming the test point e and thereference voltage VSS, the gate electrode of this transistor beingconnected onto the output of the circuit for generating the in-phasesignal and receiving the latter. The threshold inverter circuit 1 thusdelivers the inverted in-phase signal to the common point constitutingthe test point e.

With regard to the shaping inverter circuit 3, one embodiment, as shownin FIG. 2a, may include, in order to produce the single-output voltagecomparator 30, an input stage formed by a PMOS transistor, bearing thereference TP11o, connected in cascade with an NMOS transistor, bearingthe reference TN10i, the combination of these two transistors beingmounted between the supply voltage VCC and the reference voltage VSS.The common point between source electrode and drain electrode of theaforementioned transistors constitutes a test point f which is connectedto the gate electrode of the NMOS transistor TN10i. The base electrodeof the PMOS transistor TP11o forming the input stage is connected to thetest point c, that is to say to the output of the circuit 1 forgenerating the in-phase signal. Furthermore, the aforementioned inputstage is followed by an output stage formed by a PMOS transistor,referenced TP13o, and an NMOS transistor, referenced TN11i, thesetransistors being connected in cascade between the supply voltage VCCand the reference voltage VSS. The common point between source and drainelectrodes of the aforementioned transistors constitutes a test point gwhich forms the output terminal of the single-output voltage comparator.

With regard to the shaping inverter module proper, 31, this may, asshown in FIG. 2a, advantageously consist of a first and a second PMOStransistor which are connected in parallel, bearing the referenceTP1ecl, TP2ecl, between the CMOS level supply voltage VCC and a commonpoint constituting a test point h, and of an NMOS transistor, bearingthe reference TN9ecl, connected between the common point forming thetest point h and the reference voltage VSS. The gate electrodes of thePMOS transistors TP1ecl and TP2ecl and of the NMOS transistor TN9ecl areconnected to the test point g, that is to say in fact onto the output ofthe single-output voltage comparator 30. The calibrated in-phase signalis thus delivered to the common point constituting the test point h.

Finally, with regard to the output amplifier circuit 4, this may beformed by an input stage consisting of a PMOS transistor TP21o connectedin cascade with an NMOS transistor, denoted by TN5ecl, between thesupply voltage VCC and the reference voltage VSS, and by an output stageformed by a PMOS transistor, bearing the reference TP3o, mounted incascade between an NMOS transistor, TN4ecl, between the aforementionedsupply and reference voltages. The common point between source and drainelectrodes of the aforementioned transistors is connected to the commonpoint of the transistors of the input stage in order to form an outputterminal delivering the CMOS level output signal in phase with the inputsignal.

With regard to the control circuits used to reduce the steady-stateelectric-power consumption in standby mode, it should be pointed outthat these control circuits are directly integrated into eachconstituent module of the device which is the subject of the inventionas shown in FIG. 2a.

In particular, for the circuit 1 for generating an in-phase signal, thiscontrol circuit comprises two PMOS transistors, referenced TP26o, TP16o,connected in parallel, these two parallel transistors being furthermoreconnected in series with an NMOS transistor, denoted by TN13o, betweenthe supply voltage VCC and the reference voltage VSS. The gateelectrodes of these transistors are connected to an input terminal of aconsumption reduction control signal, which control signal is denoted byE.

Furthermore, a control transistor is also provided, this transistorbeing of the NMOS type, denoted by TN11o, and mounted in parallelbetween the gate electrodes of the transistors TN15i and TN12i, whichare constituents of the current generator of the attentuated currentsource 14, and the reference voltage VSS. The gate electrode of thetransistor TN11o is connected to the terminal receiving the controlsignal E.

With regard to the circuit for controlling the reduction in steady-stateelectric-power consumption within the threshold inverter circuit 2, itshould be pointed out that this consists of a PMOS-type transistor,bearing the reference tP5o, connected between the CMOS level supplyvoltage VCC and the test point c constituting the output of the circuit1 for generating an in-phase signal. The gate electrode of the PMOStransistor tP5o is connected to the common point of the PMOS transistorsTP26o and TP16o and of the NMOS transistor TN13o.

With regard to the shaping inverter circuit, it should be pointed outthat the circuit for controlling the reduction in steady-stateelectric-power consumption is incorporated into the single-outputvoltage comparator 30 and consists of an NMOS transistor, denoted byTN14o, connected between the common point forming the test point f andthe reference voltage VSS, the gate electrode of this transistor beingconnected to the terminal receiving the control signal E.

The operation of all the elements shown in FIG. 2a is as follows.

When, for example, the ECL input signal, denoted by I, rises from 3.2 Vto 4.1 V, the gate voltage of the transistors TN8ecl and TN1ecl rises asa consequence. This reduces the resistance existing between the drainand source electrodes of these two transistors. Since the currentgenerated by the constituent transistors TP18i and TP4o of the currentgenerator 110 is substantially constant, the voltage at the test point adecreases and the drain-source current of the transistor TP4eclconstituting the current generator 120 consequently increases. Since thegate voltage of the transistors TN17i and TN16i forming thevoltage-adjustable resistance 121 is constant and equal to VCC andsince, because of the fact that the TP4ecl transistor current increases,the voltage at the test point b, which is the common point 13, issubstantially fixed, the voltage at the test point c, which is the pointof output of the signal delivered by the circuit 1 for generating thein-phase signal, consequently increases, this being all the more so thehigher the resistance between the common point 13, which is the testpoint b, and the test point c. This resistance, which is adjustable,thus makes it possible to obtain a voltage gain and a modification ofthe switching point with respect to the ECL input signal, which is thesignal I.

The attenuated current source 14 allows the currents coming from theinput and amplification branches 11 and 12 to flow while at the sametime limiting their values and preventing them from going out ofbalance.

With regard to an opposite variation in the ECL input signal, that is tosay during a signal I transition from 4.1 V to 3.2 V, it is sufficientto repeat the above procedure, assuming that all of the common points ornodes change in the opposite direction to that described previously.

The attenuated current source 14 as shown in FIG. 2a operates in thefollowing manner. The transistors TN15i and TN12i have their gateelectrode connected to the test point i, that is to say to a voltagesource whose output is none other than the gate electrode of thetransistor TN215i. Since this gate is connected to the gate electrode ofthe transistors TN6i and TN9i, which are themselves connected via theirdrain electrode to the current source formed by the transistors TP8o andTP12o and in their source electrode to the resistance formed by thetransistors TP3ecl and TN7ecl, a constant voltage is developed at thetest point k, the test point j delivering a constant current to theterminals of the resistance composed of the transistors TP3ecl andTP7ecl, this voltage being constant because the gate electrodes of thelatter two transistors are connected to the reference voltage VSS and tothe CMOS level supply voltage VCC respectively. The voltage existingbetween the nodes i and k, this being the gate-source voltage of theaforementioned transistors, is constant because the current flowingthrough the transistors TN6i and TN9i is constant.

Consequently the voltage at the test point i, that is to say at thecommon point 143, is constant, the transistors TP0o and TP1o serving toconvey a current through the transistor TN25i, this current being thereverse in terms of the variations of that flowing in the transistorsTP8o and TP12o.

With regard to the threshold inverter circuit 2, this consists of ananalog inverter circuit having identical positive and negativethresholds, the threshold value being centered on the switching point ofthe output signal of the current comparator. The inverter circuit 2, asshown in FIG. 2a, is formed by the transistors TP7i, TP1ecl and TN3ecl.The voltage applied to the test point c, that is to say onto the outputof the circuit for generating an in-phase signal, is thus inverted andamplified, in terms of voltage, at the test point e. It should be notedthat these two voltages are positioned with respect to the sameswitching point. Consequently the difference between these two voltagesis either positive or negative depending on the ECL level input voltageI applied.

With regard to the shaping inverter circuit 3, it should be pointed outthat the single-output voltage comparator 30 is used to compare theinput voltage at the test point c present on the gate electrode of thetransistor TP11o with the output voltage, delivered by the invertercircuit 2, at the test point e. The single-output voltage comparator 30is formed by the transistors TP11o, TP13o, TN10i and TN11i. When thevoltage at the test point c rises whereas the voltage at the test pointe falls as a consequence, toward its lowest value, the output voltage ofthe single-output voltage comparator 30, that is to say at the testpoint g, rises and vice versa. It is therefore possible to furtherincrease the voltage gain of the entire device according to theinvention.

The shaping inverter circuit proper, 31, is used to convert the voltagevariations at the test point g into CMOS level voltage variations at thetest point h. The circuit 31 is formed by the transistors TP0ecl, TP2ecland TN9ecl. The circuit 31 is a single CMOS inverter, the switchingpoint of which is chosen to be equal to the average value of the voltageamplitude appearing at the test point g, which is the output point ofthe single-output voltage comparator 30.

Finally, the output amplifier circuit 4 is advantageously formed by aCMOS-type inverter which can be used to increase the output current uponswitching of the shaping inverter circuit 3. The output amplifiercircuit is formed by the transistors TP3o, TP21o, TN5ecl and TN4ecl. Theinput of the output amplifier 4 is formed by the test point h and theoutput terminal of the latter, delivering the CMOS level signal in phasewith the input signal, is denoted by O. The output amplifier circuitallows rapid switching of the connection line connecting the latter to aconnection matrix of a CMOS memory, for example, so as to control amemory cell of the aforementioned memory with sufficiently short riseand fall times. Consequently, the propagation time of the switchingsignals within the core of the matrix is a minimum.

With regard to the control signal for the reduction in steady-stateelectric-power consumption in standby mode, it should be pointed outthat this signal E is used not only to cut the steady-state consumptionof the four aforementioned modules, and therefore to stop themoperating, but also to generate an output CMOS level O, so as to inhibitthe steady-state electric-power consumption of the cell of theaforementioned memory matrix.

When the voltage of the control signal E is, for example, equal to 0 V,the device according to the invention operates normally, whereas forE=VCC for example, the circuit 1 for generating a signal in phase withthe input signal no longer operates because the attenuated currentsource 14 is open-circuited, as shown symbolically in FIG. 1 andphysically in FIG. 2a, the open-circuiting being performed by means ofthe transistor TN11o.

Furthermore, in the case of E=VCC, the voltage at the test point d, thatis to say on the gate electrode of the transistor P5o, is at thereference voltage VSS, i.e. 0 V, and the aforementioned transistor isconducting, which has the effect of positioning the test point c andtherefore the input of the inverter circuit 2 at the supply voltage VCC.Because of the inversion carried out by the inverter circuit 2, thevoltage at the test point e is therefore equal to the reference voltageVSS.

With regard to the shaping inverter circuit 3, when the control voltageE is equal to VCC, the transistor TN14o is turned on, which has theeffect of blocking the constituent stages of the single-output voltagecomparator 30 as well as positioning the output of the latter, that isto say the test point g, at the value of the supply voltage VCC.Consequently and because of the inversion carried out by the invertercircuit proper, 31, the output of the latter, i.e. the test point h, ispositioned at the value of the reference voltage VSS, and the outputterminal O of the amplifier circuit and of the device according to theinvention is then positioned at the supply voltage value VCC, whichcorresponds to the maximum high level in CMOS technology.

The waveforms obtained at the test points a to k in FIG. 2a for an ECLinput signal I, a control signal E and an output signal O are shown inFIGS. 2b1, 2b3 and 2b4, the abscissa axis being graduated in ns and theordinate axis in volts.

It should furthermore be pointed out that all the modules describedabove are then almost insensitive to minute variations in the width ofthe NMOS transistors used, this being an advantage when the device whichis the subject of the present invention is especially dedicated toapplications in which the operating conditions are extreme. In such acase, it is necessary in the aforementioned transistors to positiontransistor inhibit regions at the bird's beak structures, that is to saypolysilicon gate regions going from thick oxide to thin oxide, of theNMOS transistors so as to avoid the drain-source current bypassing the Ntransistor externally. Introducing these transistor inhibit regions,also called vignettes, reduces the widths of the aforementioned NMOStransistors but, on account of the fact that the overall structure isequipped with modules which are self-aligning with regard to variationin the switching thresholds, the entire structure of the deviceaccording to the invention remains operational. Furthermore, the device,which is the subject of the invention, thus constructed, with allproportions maintained, retains the same propagation-time, rise-time andfall-time electrical properties during switching events.

A particular embodiment of the ECL level/CMOS level logic-signalinterfacing device which is the subject of the present invention willnow be given in connection with FIG. 3.

This embodiment relates to a specific application in which two ECL levelsignals, denoted by I₁, and I₂ in FIG. 3, have to be converted into aCMOS level signal, the conversion criteria operating either indifferential mode or in common mode on these signals. It will berecalled that the differential mode designates the value of thedifference between the peak-to-peak amplitude between the input signalsI₁ and I₂ and that the common mode, on the other hand, designates themean value of the two aforementioned peak-to-peak amplitudes. It shouldbe pointed out that the differential mode is used when there is a givenamplitude difference between the input signals I₁ and I₂, this amplitudedifference being converted into a CMOS level logic signal by means ofthe use of the embodiment described in FIG. 3.

In the aforementioned figure, the operating units corresponding to thosein FIG. 1 or 2a, for example, bear the same references, the letter P orN being added to these references depending on whether PMOS or NMOStechnology is used to produce the corresponding parts of the device.

As will be seen in the aforementioned FIG. 3, in this embodiment theinterfacing device which is the subject of the present invention is usedto provide the interfacing for the two ECL level input signals I₁, I₂ indifferential mode and in common mode, so as to convert these signalsinto a CMOS level signal.

The device comprises, in a general manner, a first interfacing stage,denoted by I in FIG. 3, and a second interfacing stage, denoted by II inthis same figure.

Of course, the first and second interfacing stages I and II are suppliedwith a CMOS level supply voltage, the voltage VCC, relative to areference voltage VSS, as described previously in the description.

In a general manner, it should be pointed out that the first interfacingstage I advantageously comprises modules similar to those whichconstitute the embodiment of the device which is the subject of thepresent invention as described in FIG. 1 and 2a sic!.

By similar modules is meant modules which perform the same function,even if these modules have a slightly different structure. Inparticular, it should be pointed out that the first interfacing stage Iis preferably produced in PMOS technology.

It comprises, as shown in FIG. 3, a circuit, denoted by 1P, forgenerating a signal in phase with the ECL level input signals, athreshold inverter circuit 2P, a shaping inverter circuit 3P and anoutput amplifier circuit 4P, said circuits being connected in cascade.It should be pointed out that these circuits perform the same functionas those described in connection with FIGS. 1 and 2a in relation to thecreation of corresponding signals.

In particular, it should also be pointed out that in the embodimentshown in FIG. 3, the threshold inverter 2P and shaping inverter 3Pcircuits are grouped together into one and the same module, designatedby 2P, 3P, in FIG. 3.

In a nonlimiting manner, it should be pointed out that the circuit forgenerating a signal in phase with the ECL level input signals, thecircuit references 1P in FIG. 3, consists of MOS transistors denoted bytp3, tp4, tp0, tp1, tp2, tn1, tn0 and tn4.

The threshold inverter circuit and the shaping inverter circuit groupedtogether into one and the same module, bearing the references 2P and 3Pin FIG. 3 consist of the MOS transistors bearing the reference tp5, tp6,tn5 and tn6.

The output amplifier circuit 4P consists of the MOS transistors tn17,tn18, tp17 and tp18. This output amplifier circuit furthermore includesa NOT-AND type function which is used to obtain a logic level 1 when thecontrol signal E is in the zero state.

With regard to the second interfacing stage II, this is produced in NMOStechnology.

It comprises a circuit, a circuit referenced 1N, for generating a signalin phase with the ECL level input signals, a threshold inverter circuitand a shaping inverter circuit, these circuits bearing the reference 2Nand 3N respectively but being grouped together into one and the samemodule, denoted by 2N,3N in FIG. 3. The output of the shaping invertercircuit 2N,3N of the second interfacing stage II is connected to theinput of the output amplifier circuit of the first interfacing stage 4Pat the point denoted by Ob in FIG. 3.

Thus, the circuit for generating a signal in phase with the ECL levelinput signals I₁, I₂, bearing the reference 1N, consists of thetransistors tn11, tn12, tn13, tn14, tn16, tp14, tp15, tp10 and tp11, andthe threshold inverter and shaping inverter circuits 2N,3N consist ofthe transistors tn9, tn15, tp7 and tp12.

The control input E is used to control the transistors tp8 and tp7, thenthe transistors tp9 and tn9 which consist of single inverters so as tocontrol the transistors tp13, tn10 and tn3, which make it possible tocut off the supply to the circuits 1N, 1P, 2N,3N as well as 2P,3P underconditions similar to those described previously in the description. Insuch a control situation, the control signal E is in the zero state.

On the other hand, when the control input signal E is in the 1 state,the operation of the whole device in differential mode is enabled.

The embodiment described in FIG. 3 has made it possible to implement adifferential function which includes a common mode for ECL level inputsignals of between 0.8 V and 4.5 V, while the differential mode, therebeing a difference in amplitude between the two input signals I₁, I₂,was obtained for a difference value of between 100 mV to VCC. It maythus be understood that the differential mode makes it possible toconvert any difference in peak-to-peak amplitude of the two inputsignals I₁, I₂, which lies between approximately 100 mV and the value ofthe supply voltage VCC when the mean level of these signals, designatedby the common mode, is itself between 0.8 V and 4.5 V.

In the common-mode operating mode, this common mode has a fixed value of3.65 V for a non-differential input mode of 0.9 V.

From the standpoint of the general operation of the first and secondconversion stages I, II, it should be pointed out that when the commonmode of the input signals I₁, I₂ has a low value, lying between 0.8 and2 V, for example, the conversion stage I operates by means of its PMOStransistors. On the other hand, for a common mode above 2 V and up to4.5 V, the conversion stage II takes over, by means of its NMOStransistors. Thus, the conversion stages I and II operate alternatelydepending on the value of the common mode, both stages not consuming anyelectric current when not operating.

Finally, it should be pointed out that the embodiment of the interfacingcircuit which is the subject of the present invention, as shown in FIG.3, may be used so as to perform analog interfacing for circuits such asmicrocontrollers so as to allow reception of digital data emanating froman environment encoding corresponding information, in voltage andcurrent form of a varied nature. The useful information may then befound in the difference between the two input signals I₁ and I₂, forexample.

Finally, it should be pointed out that a particularly advantageousapplication relates to the detection of a voltage level of an electricsupply battery of a portable system, such as a portable computer, so asto warn the user that the supply system is deviating from its ratedvoltage value.

An ECL level/CMOS level logic-signal interfacing device has thus beendescribed which is particularly high-performance insofar as this deviceallows communication between these two logic environments under extremevoltage, temperature and operating variation conditions, without in anyway introducing a reference voltage, only small variations in theelectrical behavior of the CMOS-type transistors used being introducedin the case where such devices are intended for applications in extremeoperating conditions.

Over and above the simple character of the structure of the device andof its use, it should be pointed out that the device according to theinvention also makes it possible to save space in terms of connectionsto be made, to be easy to use and to have a low output noise levelbecause of the low strength value of the switching currents employed.

The aforementioned advantages are achieved at the price of completelyacceptable constraints such as higher heat dissipation than inconventional devices, this heat dissipation being constant however, andan arrangement of transistors whose topological characteristics are moresophisticated than the conventional-type transistors.

I claim:
 1. An ECL level/CMOS level logic-signal interfacing devicecomprising, connected in cascade and supplied with a CMOS level supplyvoltage relative to a reference voltage:a circuit for generating anin-phase signal in phase relationship with an ECL level input signal,said in-phase signal having an amplitude greater than that of said ECLlevel input signal and a mean amplitude value greater than that of saidECL level input signal; a threshold inverter circuit having a thresholdsubstantially equal to the mean amplitude value of said in-phase signal,said threshold inverter circuit receiving, on an inverting input, saidin-phase signal and delivering an inverted in-phase signal; a shapinginverter circuit receiving said inverted in-phase signal and deliveringa calibrated in-phase signal; and an output amplifier circuit receivingsaid calibrated in-phase signal and delivering an output signal, at theCMOS level, in phase relationship with said ECL level input signal. 2.The device of claim 1, wherein said circuit for generating said in-phasesignal in phase relationship with said ECL input signal comprises:acomparator circuit formed by an input branch and an amplification branchwhich are connected in parallel between said CMOS level supply voltageand a common point, said input branch and said amplification branch eachbeing formed by a current generator and a voltage-adjustable resistance,an output of said current generator of said input branch being coupledto an input for controlling said current generator of said amplificationbranch, an input for controlling the voltage-adjustable resistance ofsaid input branch being connected to an input terminal for the ECL levelinput signal and an input for controlling the adjustable resistance ofsaid amplification branch being connected to said CMOS level supplyvoltage; and an attenuated current source, connected in cascade withsaid input branch and said amplification branch in parallel, betweensaid common point and said reference voltage, said circuit forgenerating said in-phase signal delivering said in-phase signal at thepoint of connection between the current generator and thevoltage-adjustable resistance of said amplification branch.
 3. Thedevice of claim 1, wherein said threshold inverter circuitcomprises:first and second PMOS transistors connected in parallelbetween said CMOS supply voltage and a common point, said first andsecond PMOS transistors having gate electrodes connected at the outputof said circuit for generating an in-phase signal and receiving saidin-phase signal; and an NMOS transistor connected in cascade betweensaid common point and said reference voltage, said NMOS transistorhaving a gate electrode connected at the output of said circuit forgenerating an in-phase signal and receiving said in-phase signal, saidthreshold inverter circuit delivering said inverted in-phase signal atsaid common point.
 4. The device of claim 1, wherein said shapinginverter circuit comprises:a single-output voltage comparator receiving,on comparison inputs thereof, said inverted in-phase signal and saidin-phase signal, respectively, and delivering a comparison signalresulting from comparing said in-phase signal with said invertedin-phase signal; and a shaping inverter module receiving said comparisonsignal resulting from comparing said in-phase signal with said invertedin-phase signal and delivering said calibrated in-phase signal.
 5. Thedevice of claim 1, wherein said input amplifier circuit comprises:firstand second PMOS transistors connected in parallel between said CMOSlevel supply voltage and a common point; first and second NMOStransistors connected in parallel between said common point and saidreference voltage, said first and second PMOS and NMOS transistorshaving gate electrodes connected to the output of said shaping invertercircuit and receiving said calibrated in-phase signal, respectively,said common point delivering said CMOS level output signal.
 6. Thedevice of claim 1, wherein said circuit for generating an in-phasesignal, said threshold inverter circuit and said shaping circuit includea control circuit receiving a control signal for reducing thesteady-state electric-power consumption in standby mode and for applyingto the output of said amplifier circuit a CMOS level output signalproviding inhibiting of the steady-state consumption of a downstreamcircuit connected to said output of said output amplifier circuit. 7.The device of claim 2, wherein said attenuated current sourcecomprises:first and second NMOS transistors connected in parallelbetween said common point and said reference voltage; and an attenuationcontrol module delivering an attenuation control voltage to the gateelectrode of said first and second NMOS transistors.
 8. The device ofclaim 7, wherein said attenuation control module comprises:a currentsource formed by first and second PMOS transistors connected in parallelbetween said PMOS level supply voltage and a first common point, thebase electrodes of said first and second PMOS transistors beingconnected to said first common point, which delivers a constant current;a resistance formed by a PMOS transistor and a NMOS transistor connectedin parallel between second common point and said reference voltage andhaving gate electrodes connected, respectively, to said referencevoltage and to said CMOS level supply voltage; and voltage generatorcircuit formed by first and second NMOS transistors which are connectedin parallel between said first and second common points, the gateelectrodes of said first and second NMOS transistors being connected toa third common point to which are connected the gate electrodes of thefirst and second NMOS transistors forming said attenuated currentsource, said voltage generator circuit further comprising a first andsecond PMOS transistors connected in parallel between the CMOS levelsupply voltage and a fourth common point, and having gate electrodesconnected to the gate electrodes of said first and second PMOStransistors constituting said current source, said voltage generatorfurther comprising a NMOS transistor connected between said fourthcommon point and said reference voltage and having a gate electrodeconnected to said third common point and delivering said attenuationcontrol voltage.
 9. An ECL level/CMOS level logic-signal interfacingdevice for providing transmission of two ECL level input signals indifferential mode and in common mode, said device comprising first andsecond complemented interfacing stages supplied with a CMOS level supplyvoltage relative to a reference voltage, said first interfacing stage ofsaid first and second complemented interfacing stages comprising,connected in cascade:a first circuit for generating a first in-phasesignal in phase relationship with one of said two ECL level inputsignals, said first in-phase signal having an amplitude greater that ofsaid one of said two ECL level input signals and a mean amplitude valuegreater that of said ECL level input signal; a first threshold invertercircuit having threshold substantially equal to the mean amplitude valueof said first in-phase signal, said threshold inverter circuitreceiving, on an inverting input, said first in-phase signal anddelivering a first inverted in-phase signal delivering a first invertedin-phase signal; first shaping inverter circuit receiving said firstinverted in-phase signal and delivering a first calibrated in-phasesignal; and a first output amplifier circuit receiving said firstcalibrated in-phase signal and delivering an output signal at the CMOSlevel, in phase relationship with said one of said two ECL level inputsignals; and said second interfacing stage comprising, connected incascade:a second circuit for generating a second in-phase signal inphase relationship with one of said two ECL level input signals, saidsecond in-phase signal having an amplitude greater than that of said oneof said two ECL level input signals and a mean amplitude value greaterthan that of said ECL level input signal; a second threshold invertercircuit having threshold substantially equal to the mean amplitude valueof said second in-phase signal, said second threshold inverter circuitreceiving, on an inverting input, said second in-phase signal anddelivering a second inverted in-phase signal; and a second shapinginverter circuit receiving said second inverted in-phase signal anddelivering a second calibrated in-phase signal, an output of said secondshaping inverter circuit of said second interfacing stage beingconnected to an input of said first output amplifier circuit of saidfirst interfacing stage.
 10. The device of claim 9, wherein said firstinterfacing stage comprises PMOS elements, and said second interfacingstage comprises NMOS elements.